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Abstract Bayesian networks (BNs) find widespread application in many real-world probabilistic problems including diagnostics, forecasting, computer vision, etc. The basic computing primitive for BNs is a stochastic bit (s-bit) generator that can control the probability of obtaining ‘1’ in a binary bit-stream. While silicon-based complementary metal-oxide-semiconductor (CMOS) technology can be used for hardware implementation of BNs, the lack of inherent stochasticity makes it area and energy inefficient. On the other hand, memristors and spintronic devices offer inherent stochasticity but lack computing ability beyond simple vector matrix multiplication due to their two-terminal nature and rely on extensive CMOS peripherals for BN implementation, which limits area and energy efficiency. Here, we circumvent these challenges by introducing a hardware platform based on 2D memtransistors. First, we experimentally demonstrate a low-power and compact s-bit generator circuit that exploits cycle-to-cycle fluctuation in the post-programmed conductance state of 2D memtransistors. Next, the s-bit generators are monolithically integrated with 2D memtransistor-based logic gates to implement BNs. Our findings highlight the potential for 2D memtransistor-based integrated circuits for non-von Neumann computing applications. 

Two-dimensional (2D) materials offer immense potential for scientific breakthroughs and technological innovations. While early demonstrations of 2D material-based electronics, optoelectronics, flextronics, straintronics, twistronics, and biomimetic devices exploited micromechanically-exfoliated single crystal flakes, recent years have witnessed steady progress in large-area growth techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and metal–organic CVD (MOCVD). However, use of high growth temperatures, chemically-active growth precursors and promoters, and the need for epitaxy often limit direct growth of 2D materials on the substrates of interest for commercial applications. This has led to the development of a large number of methods for the layer transfer of 2D materials from the growth substrate to the target application substrate with varying degrees of cleanliness, uniformity, and transfer-related damage. This review aims to catalog and discuss these layer transfer methods. In particular, the processes, advantages, and drawbacks of various transfer methods are discussed, as is their applicability to different technological platforms of interest for 2D material implementation.